/*
 * types.h
 *
 * define some frequently-used data types
 *
 * Copyright (C) 2017 Sinh Micro, Inc.
 * Subject to the GNU Public License, version 2.
 *
 * Author: guoming<guoming@microwell.net>
 */

#ifndef __TYPES_H__
#define __TYPES_H__
#include "mcu_regs.h"

typedef unsigned char   uint8_t;
typedef char            int8_t;
typedef unsigned short  uint16_t;
typedef short           int16_t;
typedef unsigned long   uint32_t;
typedef long            int32_t;
typedef bit             bit_t;

#ifndef bool
#define bool            bit_t
#endif

#ifndef true
#define true            1
#endif

#ifndef false
#define false           0
#endif

#ifndef high
#define high            1
#endif

#ifndef low
#define low             0
#endif

#ifndef NULL
#define NULL            (0)
#endif

/**
 * @brief 整数除以整数，然后四舍五入
 * 
 */
#define ROUND_DIV(x, y) (((x) + (y) / 2L) / (y))

#define ARRAY_SIZE(a)   (sizeof(a) / sizeof((a)[0]))
#define BUFF_SIZE(buff)     (sizeof(buff) / sizeof(*buff))

#define ABS(a)          (a > 0 ? a : -a)

/**
 * @brief uint_16
 * buf[0] high 8bit
 * buf[1] low 8bit
 */
typedef union union_uint16
{
    unsigned short    u16;
    unsigned char     buf[2];
} union_uint16;

/**
 * @brief uint_16
 * buf[0] 24-31bit
 * buf[1] 16-23bit
 * buf[2] 8-15bit
 * buf[3] 0-7bit
 */
typedef union union_uint32
{
    unsigned long     u32;
    unsigned char     buf[4];
} union_uint32;

#define RESET       (0)
#define SET         (1)   

/* define eeprom registers */
#define EEPADR      (0x00)
#define EEPDAT      (0x01)
#define EEPCON      (0x02)

#define EXTMFP0     (0x12)
#define EXTMFP1     (0x13)
#define EXTMFP2     (0x74)
#define EXTMFP3     (0x75)
#define EXTMFP4     (0x76)
#define EXTMFP5     (0x77)
#define EXTMFP6     (0x6D)
#define PEXTCON0    (0x14)
#define PEXTCON1    (0x15)
#define PEXTCON2    (0x70)
#define PEXTCON3    (0x71)

#define SET_BIT(REG, BIT)     ((REG) |= (BIT))

#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))

#define READ_BIT(REG, BIT)    ((REG) & (BIT))

#define CLEAR_REG(REG)        ((REG) = (0x0))

#define WRITE_REG(REG, VAL)   ((REG) = (VAL))

#define READ_REG(REG)         ((REG))

#define MODIFY_REG(REG, CLEARMASK, SETMASK)   WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

/**
 * @brief reg enum function instructions
 * 
 */

#define    CHIP_SS880X                   (0)
#define    CHIP_SS881X                   (1)
#define    CHIP_SS888X                   (2)

#define    TICK_TIMER_ID_SYS             (0)
#define    TICK_TIMER_ID_0               (1)    
#define    TICK_TIMER_ID_1               (2)  
#define    TICK_TIMER_ID_2               (3)

/* LORC, 32KHz; HIRC, 12MHz */
#define SYS_LORC_FREQ                    (32000L)
#define SYS_4MHz_FREQ                    (4000000L)
#define SYS_12MHz_FREQ                   (12000000L)
#define SYS_HIRC_FREQ                    (12000000L)

/* Sysytem Clock DIV 1,2,3,4,8,16,32,64 */
#define    CLK_DIV_1                     (1L)
#define    CLK_DIV_2                     (2L)
#define    CLK_DIV_3                     (3L)
#define    CLK_DIV_4                     (4L)
#define    CLK_DIV_6                     (6L)
#define    CLK_DIV_8                     (8L)
#define    CLK_DIV_16                    (16L)
#define    CLK_DIV_32                    (32L)
#define    CLK_DIV_64                    (64L)

/* Timer Clock DIV 1,2,3,4,6,8,16,32 */
#define    TCLK_DIV_1                   (0x00)               // Timer0 DIV from SCLK, 1 (000)
#define    TCLK_DIV_2                   (0x02)               // Timer0 DIV from SCLK, 2 (001)
#define    TCLK_DIV_3                   (0x04)               // Timer0 DIV from SCLK, 3 (010)
#define    TCLK_DIV_4                   (0x06)               // Timer0 DIV from SCLK, 4 (011)
#define    TCLK_DIV_6                   (0x08)               // Timer0 DIV from SCLK, 6 (100)
#define    TCLK_DIV_8                   (0x0A)               // Timer0 DIV from SCLK, 8 (101)
#define    TCLK_DIV_16                  (0x0C)               // Timer0 DIV from SCLK, 16 (110)
#define    TCLK_DIV_32                  (0x0E)               // Timer0 DIV from SCLK, 32 (111)

/* Timer0 mode for 0, 1, 2, 3; Timer1 mode for 0, 1, 2;*/
#define    TIMER_13_MODE                (0x00)
#define    TIMER_16_MODE                (0x01)
#define    TIMER_8_AUTO_MODE            (0x02)
#define    TIMER_8_DIVID_MODE           (0x03)               // only for Timer0

/* uart baud rate  */
#define    UART_BAUD_RATE_4800          (0x40)              // Error range(%): 0.16
#define    UART_BAUD_RATE_9600          (0xA0)              // Error range(%): 0.16
#define    UART_BAUD_RATE_19200         (0xD0)              // Error range(%): 0.16
#define    UART_BAUD_RATE_38400         (0xE8)              // Error range(%): 2.22
#define    UART_BAUD_RATE_43000         (0xEB)              // Error range(%): 3.02
#define    UART_BAUD_RATE_56000         (0xF0)              // Error range(%): 0.16
#define    UART_BAUD_RATE_57600         (0xF0)              // Error range(%): 0.16
#define    UART_BAUD_RATE_115200        (0xF8)              // Error range(%): 0.16
#define    UART_BAUD_RATE_230400        (0xFC)              // Error range(%): 0.16
#define    UART_BAUD_RATE_460800        (0xFE)              // Error range(%): 0.16
#define    UART_BAUD_RATE_921600        (0xFF)              // Error range(%): 0.16

typedef enum
{
    HIRCEN                =  (uint8_t) (0x01),              // high RC function, disable(0), enable(1)
    HIRCSTB               =  (uint8_t) (0x02),              // high RC stable function, disable(0), enable(1)
    HIRCSSEN              =  (uint8_t) (0x04),              // high RC SSEN function, disable(0), enable(1)
} RCCON_REG;

typedef enum
{
    WAIT_1_CYCLE          =  (uint8_t) (0x10),              // Program access waits for cycles, 1 cycle(001)
    WAIT_3_CYCLE          =  (uint8_t) (0x30),              // Program access waits for cycles, 1 cycle(011)
    CLR_WAIT              =  (uint8_t) (0x70),              // Program access waits for cycles
} CKCON_REG;

typedef enum
{
    IDLE                  =  (uint8_t) (0x01),              // idle mode, enable(1), disable(0)
    STOP                  =  (uint8_t) (0x02),              // stop mode, enable(1), disable(0)
    P20WKEN               =  (uint8_t) (0x20),              // P20 wakeup enable(1), disable(0)
} PCON_REG;

typedef enum
{
    SCLKSRC_BIT           =  (uint8_t) (0x01),              // system clock source, LORC(0), HIRC(1)
    SCLKDIV_1             =  (uint8_t) (0x00),              // HIRC DIV, 1 (000)
    SCLKDIV_2             =  (uint8_t) (0x02),              // HIRC DIV, 2 (001)
    SCLKDIV_3             =  (uint8_t) (0x04),              // HIRC DIV, 3 (010)
    SCLKDIV_4             =  (uint8_t) (0x06),              // HIRC DIV, 4 (011)
    SCLKDIV_8             =  (uint8_t) (0x08),              // HIRC DIV, 8 (100)
    SCLKDIV_16            =  (uint8_t) (0x0A),              // HIRC DIV, 16 (101)
    SCLKDIV_32            =  (uint8_t) (0x0C),              // HIRC DIV, 32 (110)
    SCLKDIV_64            =  (uint8_t) (0x0E),              // HIRC DIV, 64 (111)
    SCLKDIV_CLR           =  (uint8_t) (0x0E),
    WDTWKEN_BIT           =  (uint8_t) (0x40),              // wakedog enable(1), disable(0)
    DSEN_BIT              =  (uint8_t) (0x80),              // deep sleep enable(1), disable(0)
} CLKCON0_REG;

typedef enum
{
    IIC_CE                =  (uint8_t) (0x01),              // i2c module clock enable(1), disable(0)
    SDP_CE                =  (uint8_t) (0x02),              // SDP module clock enable(1), disable(0)
    CMP_CE                =  (uint8_t) (0x04),              // CMP module clock enable(1), disable(0)
    ACC_CE                =  (uint8_t) (0x08),              // ADC&CHARGER clock module enable(1), disable(0)
    PFOU_CE               =  (uint8_t) (0x10),              // PFU souce clock module enable(1), disable(0)
    IIC_RST               =  (uint8_t) (0x40),              // IIC reset control clock module, reset after write 1
    SDP_RST               =  (uint8_t) (0x80),              // SDP reset control clock module, reset after write 1
} CLKCON1_REG;

typedef enum
{
    IIC1_CE               =  (uint8_t) (0x01),              // i2c1 module clock enable(1), disable(0)
    SPI_CE                =  (uint8_t) (0x02),              // SPI module clock enable(1), disable(0)
    UART1_CE              =  (uint8_t) (0x04),              // UART1 module clock enable(1), disable(0)
    SSP_CE                =  (uint8_t) (0x08),              // SSP clock module enable(1), disable(0)
    IIC1_RST              =  (uint8_t) (0x10),              // IIC1 reset control clock module, reset after write 1
    SPI_RST               =  (uint8_t) (0x20),              // SPI reset control clock module, reset after write 1
    UART1_RST             =  (uint8_t) (0x40),              // UART1 reset control clock module, reset after write 1
    SSP_RST               =  (uint8_t) (0x80),              // SDP reset control clock module, reset after write 1
} CLKCON2_REG;

typedef enum
{
    CMP0EN                =  (uint8_t) (0x01),              // CMP0 module enable(1), disable(0)
    CMP0P_GND             =  (uint8_t) (0x00),              // CMP0 Positive end input tap configuration, GND (000)
    CMP0P_CMP1            =  (uint8_t) (0x02),              // CMP0 Positive end input tap configuration, CMP1 (001)
    CMP0P_V15             =  (uint8_t) (0x04),              // CMP0 Positive end input tap configuration, 0.15V (010)
    CMP0P_0V3             =  (uint8_t) (0x06),              // CMP0 Positive end input tap configuration, 0.3V (011)
    CMP0P_0V6             =  (uint8_t) (0x08),              // CMP0 Positive end input tap configuration, 0.6V (100)
    CMP0P_0V9             =  (uint8_t) (0x0A),              // CMP0 Positive end input tap configuration, 0.9V (101)
    CMP0P_1V2             =  (uint8_t) (0x0C),              // CMP0 Positive end input tap configuration, 1.2V (110)
    CMP0P_1V5             =  (uint8_t) (0x0E),              // CMP0 Positive end input tap configuration, VREF(1.5V) (111)
    CMP1EN                =  (uint8_t) (0x10),              // CMP1 module enable(1), disable(0)
    CMP1P_GND             =  (uint8_t) (0x00),              // CMP1 Positive end input tap configuration, GND (000)
    CMP1P_CMP0            =  (uint8_t) (0x20),              // CMP1 Positive end input tap configuration, CMP1 (001)
    CMP1P_V15             =  (uint8_t) (0x40),              // CMP1 Positive end input tap configuration, 0.15V (010)
    CMP1P_0V3             =  (uint8_t) (0x60),              // CMP1 Positive end input tap configuration, 0.3V (011)
    CMP1P_0V6             =  (uint8_t) (0x80),              // CMP1 Positive end input tap configuration, 0.6V (100)
    CMP1P_0V9             =  (uint8_t) (0xA0),              // CMP1 Positive end input tap configuration, 0.9V (101)
    CMP1P_1V2             =  (uint8_t) (0xC0),              // CMP1 Positive end input tap configuration, 1.2V (110)
    CMP1P_1V5             =  (uint8_t) (0xE0),              // CMP1 Positive end input tap configuration, VREF(1.5V) (111)
    CLEAR_CMPCON0_BIT     = (uint8_t) (0xFF)
} CMPCON0_REG;

typedef enum
{
    CMP0DE_1_SCLK         =  (uint8_t) (0x00),              // CMP0 Output status Debounce time (in SCKL), 1 SCLK cycle(000)
    CMP0DE_3_SCLK         =  (uint8_t) (0x01),              // CMP0 Output status Debounce time (in SCKL), 3 SCLK cycle(001)
    CMP0DE_7_SCLK         =  (uint8_t) (0x02),              // CMP0 Output status Debounce time (in SCKL), 7 SCLK cycle(010)
    CMP0DE_31_SCLK        =  (uint8_t) (0x03),              // CMP0 Output status Debounce time (in SCKL), 31 SCLK cycle(011)
    CMP0DE_127_SCLK       =  (uint8_t) (0x04),              // CMP0 Output status Debounce time (in SCKL), 127 SCLK cycle(100)
    CMP0DE_255_SCLK       =  (uint8_t) (0x05),              // CMP0 Output status Debounce time (in SCKL), 255 SCLK cycle(101)
    CMP0DE_3_32K          =  (uint8_t) (0x06),              // CMP0 Output status Debounce time (in SCKL), 3 32KHz cycle(110)
    CMP0DE_7_32K          =  (uint8_t) (0x07),              // CMP0 Output status Debounce time (in SCKL), 7 32KHz cycle(111)
    CMP1DE_1_SCLK         =  (uint8_t) (0x00),              // CMP1 Output status Debounce time (in SCKL), 1 SCLK cycle(000)
    CMP1DE_3_SCLK         =  (uint8_t) (0x10),              // CMP1 Output status Debounce time (in SCKL), 3 SCLK cycle(001)
    CMP1DE_7_SCLK         =  (uint8_t) (0x20),              // CMP1 Output status Debounce time (in SCKL), 7 SCLK cycle(010)
    CMP1DE_15_SCLK        =  (uint8_t) (0x30),              // CMP1 Output status Debounce time (in SCKL), 15 SCLK cycle(011)
    CMP1DE_31_SCLK        =  (uint8_t) (0x40),              // CMP1 Output status Debounce time (in SCKL), 31 SCLK cycle(100)
    CMP1DE_63_SCLK        =  (uint8_t) (0x50),              // CMP1 Output status Debounce time (in SCKL), 63 SCLK cycle(101)
    CMP1DE_127_SCLK       =  (uint8_t) (0x60),              // CMP1 Output status Debounce time (in SCKL), 127 SCLK cycle(110)
    CMP1DE_255_SCLK       =  (uint8_t) (0x70),              // CMP1 Output status Debounce time (in SCKL), 255 SCLKz cycle(111)
    CLEAR_CMPCON1_BIT     =  (uint8_t) (0x77)
} CMPCON1_REG;

typedef enum
{
    CMP0IM_NOT            =  (uint8_t) (0x00),              // CMP0 interrupt condition setting, no occus(00)
    CMP0IM_0_1            =  (uint8_t) (0x01),              // CMP0 interrupt condition setting, 0-->1(01)
    CMP0IM_1_0            =  (uint8_t) (0x02),              // CMP0 interrupt condition setting, 1-->0(10)
    CMP0IM_ALL            =  (uint8_t) (0x03),              // CMP0 interrupt condition setting, 1-->0 or 0-->1(11)
    RESULT0               =  (uint8_t) (0x04),              // CMP0 Output result, Positive < negative(0), Positive > negative(1)
    CMP0F                 =  (uint8_t) (0x08),              // CMP0 Output Interrupt flag bit, occus (1), or not(0)
    CMP1IM_NOT            =  (uint8_t) (0x00),              // CMP1 interrupt condition setting, no occus(00)
    CMP1IM_0_1            =  (uint8_t) (0x10),              // CMP1 interrupt condition setting, 0-->1(01)
    CMP1IM_1_0            =  (uint8_t) (0x20),              // CMP1 interrupt condition setting, 1-->0(10)
    CMP1IM_ALL            =  (uint8_t) (0x30),              // CMP1 interrupt condition setting, 1-->0 or 0-->1(11)
    RESULT1               =  (uint8_t) (0x40),              // CMP1 Output result, Positive < negative(0), Positive > negative(1)
    CMP1F                 =  (uint8_t) (0x80),              // CMP1 Output Interrupt flag bit, occus (1), or not(0)
    CLEAR_CMPCON2_BIT     =  (uint8_t) (0xFF)
} CMPCON2_REG;

typedef enum
{
    P03WKEN               =  (uint8_t) (0x20),              // P03 wakeup enable(1), disable(0)
    P04WKEN               =  (uint8_t) (0x40),              // P04 wakeup enable(1), disable(0)
    P06WKEN               =  (uint8_t) (0x80),              // P06 wakeup enable(1), disable(0)
} P1MOD_REG;

typedef enum
{
    P03WKEM               =  (uint8_t) (0x20),              // P03 wakeup mode high(1), low(0)
    P04WKEM               =  (uint8_t) (0x40),              // P04 wakeup mode high(1), low(0)
    DRV07MOD              =  (uint8_t) (0x80),              // P07 source and sink, normal(0), plus(1)
} P1OM_REG;

typedef enum
{
    P06WKM_LL             =  (uint8_t) (0x00),              // P06 low level, wakeup enable(00)
    P06WKM_HL             =  (uint8_t) (0x40),              // P06 high level, wakeup enable(01)
    P06WKM_FE             =  (uint8_t) (0x80),              // P06 low edge, wakeup enable(10)
    P06WKM_RE             =  (uint8_t) (0xC0),              // P06 high edge, wakeup enable(11)
    P06WKM_CLR            =  (uint8_t) (0xC0),              // P06 high edge, wakeup enable(11)
} MFP3_REG;

typedef enum
{
    P07WKM_LL             =  (uint8_t) (0x01),              // P07 low level, wakeup enable(001), disable(0)
    P07WKM_HL             =  (uint8_t) (0x02),              // P07 high level, wakeup enable(010), disable(0)
    P07WKM_FE             =  (uint8_t) (0x03),              // P07 low edge, wakeup enable(011), disable(0)
    P07WKM_RE             =  (uint8_t) (0x04),              // P07 high edge, wakeup enable(100), disable(0)
    P07WKM_LP             =  (uint8_t) (0x05),              // P07 high edge, wakeup enable(101), disable(0)
    P07WKM_HP             =  (uint8_t) (0x06),              // P07 high edge, wakeup enable(110), disable(0)
    P07WKM_CLR            =  (uint8_t) (0x07),              // P07 high edge, wakeup, disable(000)(111)
    P11WKM_LL             =  (uint8_t) (0x08),              // P11 low level, wakeup enable(001), disable(0)
    P11WKM_HL             =  (uint8_t) (0x10),              // P11 high level, wakeup enable(010), disable(0)
    P11WKM_FE             =  (uint8_t) (0x18),              // P11 low edge, wakeup enable(011), disable(0)
    P11WKM_RE             =  (uint8_t) (0x20),              // P11 high edge, wakeup enable(100), disable(0)
    P11WKM_LP             =  (uint8_t) (0x28),              // P11 high edge, wakeup enable(101), disable(0)
    P11WKM_HP             =  (uint8_t) (0x30),              // P11 high edge, wakeup enable(110), disable(0)
    P11WKM_CLR            =  (uint8_t) (0x38),              // P11 high edge, wakeup, disable(000)(111)
    P07WKF                =  (uint8_t) (0x40),              // P07 wakeup flag, wakeup(1), or not(0)
    P11WKF                =  (uint8_t) (0x80),              // P11 wakeup flag, wakeup(1), or not(0)
} PWKCTL_REG;

typedef enum
{
    OVDSET                =  (uint8_t) (0x01),              // over voltage set, 0: protect > 5.6V, restore < 5.4V; 1: protect > 6V, restore < 5.6V
    LVLDOEN               =  (uint8_t) (0x02),              // when low voltage and vinOk, inner-ldo enable(1) , inner-ldo disable(0) 
    OVDEN                 =  (uint8_t) (0x04),              // over voltage function, disable(0), enable(1)
    CLEAR_OVD             =  (OVDSET|OVDEN),
} PWRCON1_REG;

typedef enum
{
    LVDEN                 =  (uint8_t) (0x01),              // vdd low voltage detect function, enable(1), disable(0)
    VKEYWKY               =  (uint8_t) (0x02),              // vkey wakeup flag, enable(1), disable(0)
    LVREN                 =  (uint8_t) (0x04),              // when vdd low voltage and LVDEN(1), reset function enable(1), disable(0)
    LVDSET_3V             =  (uint8_t) (0x10),              // vdd low voltage detect set, 3V(010)
    LVDSET_3V3            =  (uint8_t) (0x18),              // vdd low voltage detect set, 3.3V(011)
    LVDSET_3V4            =  (uint8_t) (0x20),              // vdd low voltage detect set, 3.4V(100)
    LVDSET_3V5            =  (uint8_t) (0x28),              // vdd low voltage detect set, 3.5V(101)
    LVDSET_3V6            =  (uint8_t) (0x30),              // vdd low voltage detect set, 3.6V(110)
    LVDSET_4V1            =  (uint8_t) (0x38),              // vdd low voltage detect set, 4.1V(111)
    LVRSET_2V5            =  (uint8_t) (0x00),              // vdd low voltage set, 2.5V(00)
    LVRSET_2V8            =  (uint8_t) (0x40),              // vdd low voltage set, 2.8V(01)
    LVRSET_3V15           =  (uint8_t) (0x80),              // vdd low voltage set, 3.15V(10)
    LVRSET_3V85           =  (uint8_t) (0xC0),              // vdd low voltage set, 3.85V(11)
    CLR_LV_STU            =  (LVDEN|LVREN|LVDSET_4V1|LVRSET_3V85),
    LV_STU                =  (LVDEN|LVREN|LVDSET_3V|LVRSET_2V5),
} PWRCON2_REG;

typedef enum
{
    /** TODO: **/
    PWRCON3_NO_USE,
} PWRCON3_REG;

typedef enum
{
    OTIF                  =  (uint8_t) (0x01),              // Overtemperature interrupt flag bit, occus(1), or not(0)
    HTSET                 =  (uint8_t) (0x02),              // high  Overtemperature, 0: protect > 130C, restore < 80C; 1: protect > 140C, restore < 80C
    OTSET                 =  (uint8_t) (0x04),              // Overtemperature, 0: protect > 110C, restore < 90C; 1: protect > 120C, restore < 90C
    OTDEN                 =  (uint8_t) (0x08),              // Overtemperature detection is enable(1), disable(0)
    DCINWKF               =  (uint8_t) (0x20),              // DCIN wakeup flag, DCIN(1), NO DCIN(0)
    VINEN                 =  (uint8_t) (0x40),              // DCIN control, disable(0), enable(1)
    VINENF                =  (uint8_t) (0x80),              // VIN flag status, close(0), open(1)
} PWRCON4_REG;

typedef enum
{
    DCINOK                =  (uint8_t) (0x01),              // DCIN Flag, 0: dcin < 3.6 or vin < vbat; 1: dcin > 4.5 or vin > vbat
    VKEYSTAT              =  (uint8_t) (0x02),              // Vkey inserts interrupt pending bits, occus(1), or not(0)
    OVDIF                 =  (uint8_t) (0x04),              // DCIN ovp inserts interrupt pending bits, occus(1), or not(0)
    VINOK                 =  (uint8_t) (0x08),              // VIN Flag, 0: vin < 3.6 or vin < vbat; 1: vin > 4.5 or vin > vbat
    LVDIF                 =  (uint8_t) (0x10),              // VDD lvp inserts interrupt pending bits, occus(1), or not(0)
    OCDIF                 =  (uint8_t) (0x20),              // VIN OCP inserts interrupt pending bits, occus(1), or not(0)
} PWRSTAT_REG;

typedef enum
{
    CHG_EN                =  (uint8_t) (0x01),              // Charging module control, enable(1), diable(0)
    FORCEEN               =  (uint8_t) (0x02),              // Force charging module control, enable(1), diable(0)
    TIMEOUT_08H           =  (uint8_t) (0x00),              // charging timeout, 8h(00)
    TIMEOUT_12H           =  (uint8_t) (0x04),              // charging timeout, 8h(01)
    TIMEOUT_24H           =  (uint8_t) (0x08),              // charging timeout, 8h(10)
    TIMEOUT_48H           =  (uint8_t) (0x0C),              // charging timeout, 8h(11)
    TIMEOUT_CLR           =  (uint8_t) (0x0C),              // charging timeout, 8h(11)
    ISET_45               =  (uint8_t) (0x00),              // charging current set, 45ma(0000)
    ISET_90               =  (uint8_t) (0x10),              // charging current set, 90ma(0001)
    ISET_135              =  (uint8_t) (0x20),              // charging current set, 135ma(0010)
    ISET_180              =  (uint8_t) (0x30),              // charging current set, 180ma(0011)
    ISET_225              =  (uint8_t) (0x40),              // charging current set, 225ma(0100)
    ISET_270              =  (uint8_t) (0x50),              // charging current set, 270ma(0101)
    ISET_315              =  (uint8_t) (0x60),              // charging current set, 315ma(0110)
    ISET_360              =  (uint8_t) (0x70),              // charging current set, 360ma(0111)
    ISET_405              =  (uint8_t) (0x80),              // charging current set, 405ma(1000)
    ISET_450              =  (uint8_t) (0x90),              // charging current set, 450ma(1001)
    ISET_495              =  (uint8_t) (0xA0),              // charging current set, 495ma(1010)
    ISET_540              =  (uint8_t) (0xB0),              // charging current set, 540ma(1011)
    ISET_585              =  (uint8_t) (0xC0),              // charging current set, 585ma(1100)
    ISET_630              =  (uint8_t) (0xD0),              // charging current set, 630ma(1101)
    ISET_675              =  (uint8_t) (0xE0),              // charging current set, 675ma(1110)
    ISET_720              =  (uint8_t) (0xF0),              // charging current set, 720ma(1111)
    CLR_ISET              =  (uint8_t) (0xF0),
} CHGCON0_REG;

typedef enum
{
    ISTOPEN               =  (uint8_t) (0x01),              // Charging module control, enable(1), diable(0)
    TLPEN                 =  (uint8_t) (0x02),              // Force charging module control, enable(1), diable(0)
    VLPEN                 =  (uint8_t) (0x04),              // Voltage loop module control, enable(1), diable(0)
    VSET_4V10             =  (uint8_t) (0xA8),              // charging voltage set, 4.1V(10101)
    VSET_4V20             =  (uint8_t) (0xB8),              // charging voltage set, 4.2V(10111)
    VSET_4V25             =  (uint8_t) (0xC0),              // charging current set, 4.25V(11000)
    VSET_4V30             =  (uint8_t) (0xC8),              // charging current set, 4.3V(11001)
    VSET_4V35             =  (uint8_t) (0xD0),              // charging current set, 4.35V(11010)
    VSET_4V40             =  (uint8_t) (0xD8),              // charging current set, 4.4V(11011)
    VSET_4V45             =  (uint8_t) (0xE0),              // charging current set, 4.45V(11100)
    VSET_4V50             =  (uint8_t) (0xE8),              // charging current set, 4.5V(11101)
    CLR_VSET              =  (uint8_t) (0xF8),
} CHGCON1_REG;

typedef enum
{
    ISTOP_5               =  (uint8_t) (0x01),              // Full current threshold, 5%(01)
    ISTOP_10              =  (uint8_t) (0x03),              // Full current threshold, 10%(11)
    VSTOP_30              =  (uint8_t) (0x08),              // Full voltage threshold, 30mv(10)
    VSTOP_60              =  (uint8_t) (0x04),              // Full voltage threshold, 60mv(01)
    TLPSET_95             =  (uint8_t) (0x00),              // Temperature threshold of full loop, 95C(00)
    TLPSET_105            =  (uint8_t) (0x10),              // Temperature threshold of full loop, 105C(01)
    TLPSET_115            =  (uint8_t) (0x20),              // Temperature threshold of full loop, 115C(10)
    TLPSET_125            =  (uint8_t) (0x30),              // Temperature threshold of full loop, 125C(11)
    VLPSET_4V4            =  (uint8_t) (0x00),              // Undervoltage loop voltage threshold, 4.4V(00)
    VLPSET_4V5            =  (uint8_t) (0x40),              // Undervoltage loop voltage threshold, 4.5V(01)
    VLPSET_4V6            =  (uint8_t) (0x80),              // Undervoltage loop voltage threshold, 4.6V(10)
    VLPSET_4V7            =  (uint8_t) (0xC0),              // Undervoltage loop voltage threshold, 4.7V(11)
} CHGCON2_REG;

typedef enum
{
    IMOD                  =  (uint8_t) (0x02),              // Force charging module control, enable(1), diable(0)
    CHGMOD                =  (uint8_t) (0x08),              // charging mode, charge(10)
    LDOMOD                =  (uint8_t) (0x0C),              // charging mode, ldo(11)
    CHGMOD_CLR            =  (uint8_t) (0x0C),
    IPLUS200              =  (uint8_t) (0x80),              // charging current all add 200ma, enable(1), disable(0)
} CHGCON3_REG;

typedef enum
{
    PCVEN                 =  (uint8_t) (0x01),              // Intermittent constant voltage charging, enable(1), diable(0)
    CHGIE                 =  (uint8_t) (0x02),              // Charge timeout or full, send interrupt, enable(1), diable(0)
    RCHG                  =  (uint8_t) (0x04),              // Recharger, enable(1), diable(0)
    BATDETEN              =  (uint8_t) (0x10),              // Battery detection enable(1), diable(0)
    DCINIF                =  (uint8_t) (0x20),              // DCIN inserts interrupt pending bits, occus(1), or not(0)
    DCINWKEN              =  (uint8_t) (0x40),              // DCIN insert wake up is enabled, enable(1), disable(0)
    DCINWKM               =  (uint8_t) (0x80),              // DCIN insertion wake-up mode, DCIN(1), DCOUT/IN(0)
} CHGCON4_REG;

typedef enum
{
    CHGON                 =  (uint8_t) (0x08),              // is charging, charging(1), or not(0)
    CHGFULL               =  (uint8_t) (0x10),              // is charging full, full(1), or not(0)
    CHGTO                 =  (uint8_t) (0x20),              // is charging timeout, timeout(1), or not(0)
    CHGTK                 =  (uint8_t) (0x40),              // is trickle charging, trickle(1), or not(0)
    CHGIF                 =  (uint8_t) (0x80),              // is Charging timeout or full , interrupt(1), or not(0)
} CHGSTAT_REG;

typedef enum
{
    EUART_BIT             =  (uint8_t) (0x01),              // Uart interrupt enable bit, enable(1), disable(0)
    EIIC_BIT              =  (uint8_t) (0x02),              // IIC interrupt enable bit, enable(1), disable(0)
    EOT_BIT               =  (uint8_t) (0x04),              // Over temperature interrupt enable bit, enable(1), disable(0)
    ELV_BIT               =  (uint8_t) (0x08),              // Low VDD interrupt enable bit, enable(1), disable(0)
    ETS_BIT               =  (uint8_t) (0x10),              // touch source interrupt enable bit, enable(1), disable(0)
    ECMP_BIT              =  (uint8_t) (0x20),              // CMP interrupt enable bit, enable(1), disable(0)
    ECHG_BIT              =  (uint8_t) (0x40),              // Charger interrupt enable bit, enable(1), disable(0)
    EA_BIT                =  (uint8_t) (0x80),              // All interrupt enable bit, enable(1), disable(0)
} INTEN0_REG;

typedef enum
{
    ET2C0_BIT             =  (uint8_t) (0x01),              // Timer2 capture 0 interrupt enable bit, enable(1), disable(0)
    ET2C1_BIT             =  (uint8_t) (0x02),              // Timer2 capture 1 interrupt enable bit, enable(1), disable(0)
    ET2C2_BIT             =  (uint8_t) (0x04),              // Timer2 capture 2 interrupt enable bit, enable(1), disable(0)
    ET2C3_BIT             =  (uint8_t) (0x08),              // Timer2 capture 3 interrupt enable bit, enable(1), disable(0)
    ET2_BIT               =  (uint8_t) (0x10),              // Timer2 counter interrupt enable bit, enable(1), disable(0)
    ET1_BIT               =  (uint8_t) (0x20),              // Timer1 counter interrupt enable bit, enable(1), disable(0)
    ET0_BIT               =  (uint8_t) (0x40),              // Timer0 counter interrupt enable bit, enable(1), disable(0)
    ESDP_BIT              =  (uint8_t) (0x80),              // SDP interface interrupt enable bit, enable(1), disable(0)
} INTEN1_REG;


typedef enum
{
    EX0_BIT               =  (uint8_t) (0x01),              // Ext 0 interrupt enable bit, enable(1), disable(0)
    EX1_BIT               =  (uint8_t) (0x02),              // Ext 1  interrupt enable bit, enable(1), disable(0)
    EADC_BIT              =  (uint8_t) (0x04),              // ADC interrupt enable bit, enable(1), disable(0)
    EOV_BIT               =  (uint8_t) (0x08),              // DCIN over Voltage interrupt enable bit, enable(1), disable(0)
    EOC_BIT               =  (uint8_t) (0x10),              // DCIN over Current interrupt enable bit, enable(1), disable(0)
    ETICK_BIT             =  (uint8_t) (0x20),              // system tick counter interrupt enable bit, enable(1), disable(0)
    ESPP_BIT              =  (uint8_t) (0x40),              // SPP interrupt enable bit, enable(1), disable(0)
} INTEN2_REG;

typedef enum
{
    EUART1_BIT            =  (uint8_t) (0x01),              // EUART1 interrupt enable bit, enable(1), disable(0)
    EIIC1_BIT             =  (uint8_t) (0x02),              // EIIC1 interrupt enable bit, enable(1), disable(0)
    ESPI_BIT              =  (uint8_t) (0x04),              // ESPI interrupt enable bit, enable(1), disable(0)
    ESSP_BIT              =  (uint8_t) (0x08),              // ESSP interrupt enable bit, enable(1), disable(0))
} INTEN3_REG;

typedef enum
{
    TICKEN_BIT            =  (uint8_t) (0x01),              // SysTick module enable(1), disable(0)
    TICKIF_BIT            =  (uint8_t) (0x10),              // SysTick overflows the flag bit, overflows(1), or not(0)
    PERIOD_10             =  (uint8_t) (0x00),              // Systick Periodic selection, 10ms (000)
    PERIOD_20             =  (uint8_t) (0x20),              // Systick Periodic selection, 20ms (001)
    PERIOD_50             =  (uint8_t) (0x40),              // Systick Periodic selection, 50ms (010)
    PERIOD_100            =  (uint8_t) (0x60),              // Systick Periodic selection, 100ms (011)
    PERIOD_200            =  (uint8_t) (0x80),              // Systick Periodic selection, 200ms (100)
    PERIOD_500            =  (uint8_t) (0xA0),              // Systick Periodic selection, 500ms (101)
    PERIOD_800            =  (uint8_t) (0xC0),              // Systick Periodic selection, 800ms (110)
    PERIOD_1000           =  (uint8_t) (0xE0),              // Systick Periodic selection, 1000ms (111)
} TICKCON_REG;

typedef enum
{
    TBLNE0_BIT            =  (uint8_t) (0x01),              // PWM0 breath mode enable(1), disable(0)
    TPE0_BIT              =  (uint8_t) (0x02),              // PWM0 mode enable(1), disable(0)
    TR0_BIT               =  (uint8_t) (0x04),              // Timer0 enable(1), disable(0)
    TF0_BIT               =  (uint8_t) (0x08),              // Timer0 overflows the flag bit, overflows(1), or not(0)
    TBLNE1_BIT            =  (uint8_t) (0x10),              // PWM1 breath mode enable(1), disable(0)
    TPE1_BIT              =  (uint8_t) (0x20),              // PWM1 mode enable(1), disable(0)
    TR1_BIT               =  (uint8_t) (0x40),              // Timer1 enable(1), disable(0)
    TF1_BIT               =  (uint8_t) (0x80),              // Timer1 overflows the flag bit, overflows(1), or not(0)
} TCON_REG;

typedef enum
{
    TPS0                  =  (uint8_t) (0x01),              // PWM0 Output polarity control, high(1), low(0)
    TCLKDIV0_1            =  (uint8_t) (0x00),              // Timer0 DIV from SCLK, 1 (000)
    TCLKDIV0_2            =  (uint8_t) (0x02),              // Timer0 DIV from SCLK, 2 (001)
    TCLKDIV0_3            =  (uint8_t) (0x04),              // Timer0 DIV from SCLK, 3 (010)
    TCLKDIV0_4            =  (uint8_t) (0x06),              // Timer0 DIV from SCLK, 4 (011)
    TCLKDIV0_6            =  (uint8_t) (0x08),              // Timer0 DIV from SCLK, 6 (100)
    TCLKDIV0_8            =  (uint8_t) (0x0A),              // Timer0 DIV from SCLK, 8 (101)
    TCLKDIV0_16           =  (uint8_t) (0x0C),              // Timer0 DIV from SCLK, 16 (110)
    TCLKDIV0_32           =  (uint8_t) (0x0E),              // Timer0 DIV from SCLK, 32 (111)
    TCLKDIV0_CLR          =  (uint8_t) (0x0E),
    TPS1                  =  (uint8_t) (0x10),              // PWM1 Output polarity control, high(1), low(0)
    TCLKDIV1_1            =  (uint8_t) (0x00),              // Timer1 DIV from SCLK, 1 (000)
    TCLKDIV1_2            =  (uint8_t) (0x20),              // Timer1 DIV from SCLK, 2 (001)
    TCLKDIV1_3            =  (uint8_t) (0x40),              // Timer1 DIV from SCLK, 3 (010)
    TCLKDIV1_4            =  (uint8_t) (0x60),              // Timer1 DIV from SCLK, 4 (011)
    TCLKDIV1_6            =  (uint8_t) (0x80),              // Timer1 DIV from SCLK, 6 (100)
    TCLKDIV1_8            =  (uint8_t) (0xA0),              // Timer1 DIV from SCLK, 8 (101)
    TCLKDIV1_16           =  (uint8_t) (0xC0),              // Timer1 DIV from SCLK, 16 (110)
    TCLKDIV1_32           =  (uint8_t) (0xE0),              // Timer1 DIV from SCLK, 32 (111)
    TCLKDIV1_CLR          =  (uint8_t) (0xE0),
} TCON1_REG;

typedef enum 
{
    M0_13_BIT             =  (uint8_t) (0x00),              // Timer0 Mode0 selection, ignore TL0:bit5-7, 13bit Timer/Counter enable(00)
    M0_16_BIT             =  (uint8_t) (0x01),              // Timer0 Mode1 selection, 16bit Timer/Counter enable(01)
    M0_A8_BIT             =  (uint8_t) (0x02),              // Timer0 Mode2 selection, auto 8bit Timer/Counter enable(10)
    M0_D8_BIT             =  (uint8_t) (0x03),              // Timer0 Mode3 selection, divid 8bit Timer enable(11), only for Timer0
    M0_CLR_BIT            =  (uint8_t) (0x03),
    C_T0_BIT              =  (uint8_t) (0x04),              // Timer0/Counter0 mode,  Counter(1), Timer(0)
    GATE0_BIT             =  (uint8_t) (0x08),              // Timer0 enable(1), disable(0)

    M1_13_BIT             =  (uint8_t) (0x00),              // Timer1 Mode0 selection, ignore TL0:bit5-7, 13bit Timer/Counter enable(00)
    M1_16_BIT             =  (uint8_t) (0x10),              // Timer1 Mode1 selection, 16bit Timer/Counter enable(01)
    M1_A8_BIT             =  (uint8_t) (0x20),              // Timer1 Mode2 selection, auto 8bit Timer/Counter enable(10)
    M1_CLR_BIT            =  (uint8_t) (0x30),
    C_T1_BIT              =  (uint8_t) (0x40),              // Timer1/Counter1 mode,  Counter(1), Timer(0)
    GATE1_BIT             =  (uint8_t) (0x80),              // Timer1 enable(1), disable(0)
} TMOD_REG;


typedef enum
{
    TCCS0_BIT             =  (uint8_t) (0x01),              // CC0, after the timer overflows, the output low level(1), normal(0); capture function starts, falling edge(1), rising edge(0)
    TCCS1_BIT             =  (uint8_t) (0x02),              // CC1, after the timer overflows, the output low level(1), normal(0); capture function starts, falling edge(1), rising edge(0)
    TCCS2_BIT             =  (uint8_t) (0x04),              // CC2, after the timer overflows, the output low level(1), normal(0); capture function starts, falling edge(1), rising edge(0)
    TCCS3_BIT             =  (uint8_t) (0x08),              // CC3, after the timer overflows, the output low level(1), normal(0); capture function starts, falling edge(1), rising edge(0)

    TR2_BIT               =  (uint8_t) (0x10),              // Timer2 enable(1), disable(0)
    TCLKDIV2_1            =  (uint8_t) (0x00),              // Timer2 DIV from SCLK, 1 (000)
    TCLKDIV2_2            =  (uint8_t) (0x20),              // Timer2 DIV from SCLK, 2 (001)
    TCLKDIV2_3            =  (uint8_t) (0x40),              // Timer2 DIV from SCLK, 3 (010)
    TCLKDIV2_4            =  (uint8_t) (0x60),              // Timer2 DIV from SCLK, 4 (011)
    TCLKDIV2_6            =  (uint8_t) (0x80),              // Timer2 DIV from SCLK, 6 (100)
    TCLKDIV2_8            =  (uint8_t) (0xA0),              // Timer2 DIV from SCLK, 8 (101)
    TCLKDIV2_16           =  (uint8_t) (0xC0),              // Timer2 DIV from SCLK, 16 (110)
    TCLKDIV2_32           =  (uint8_t) (0xE0),              // Timer2 DIV from SCLK, 32 (111)
    TCLKDIV2_CLR          =  (uint8_t) (0xE0),
} T2CON_REG;

typedef enum 
{
    TCCM0_NONE            =  (uint8_t) (0x00),              // CC0 mode selector, disable(00)
    TCCM0_CA              =  (uint8_t) (0x01),              // CC0 mode selector, capture enable(01)
    TCCM0_CO              =  (uint8_t) (0x02),              // CC0 mode selector, compare enable(10)
    TCCM1_NONE            =  (uint8_t) (0x00),              // CC1 mode selector, disable(00)
    TCCM1_CA              =  (uint8_t) (0x04),              // CC1 mode selector, capture enable(01)
    TCCM1_CO              =  (uint8_t) (0x08),              // CC1 mode selector, compare enable(10)
    TCCM2_NONE            =  (uint8_t) (0x00),              // CC2 mode selector, disable(00)
    TCCM2_CA              =  (uint8_t) (0x10),              // CC2 mode selector, capture enable(01)
    TCCM2_CO              =  (uint8_t) (0x20),              // CC2 mode selector, compare enable(10)
    TCCM3_NONE            =  (uint8_t) (0x00),              // CC3 mode selector, disable(00)
    TCCM3_CA              =  (uint8_t) (0x40),              // CC3 mode selector, capture enable(01)
    TCCM3_CO              =  (uint8_t) (0x80),              // CC3 mode selector, compare enable(10)
} T2MOD_REG;

typedef enum 
{
    TF2_BIT               =  (uint8_t) (0x10),              // Timer2 overflows the flag bit, overflows(1), or not(0)
} T2STAT_REG;


typedef enum
{
    ADCCON0_RESET,
    FILTER_4              = (uint8_t) (0x00),     // After ADC sampling, filter the average number of samples (000)
    FILTER_16             = (uint8_t) (0x02),     // After ADC sampling, filter the average number of samples (001)
    FILTER_32             = (uint8_t) (0x04),     // After ADC sampling, filter the average number of samples (010)
    FILTER_64             = (uint8_t) (0x06),     // After ADC sampling, filter the average number of samples (011)
    FILTER_128            = (uint8_t) (0x08),     // After ADC sampling, filter the average number of samples (100)
    FILTER_256            = (uint8_t) (0x0A),     // After ADC sampling, filter the average number of samples (101)
    FILTER_512            = (uint8_t) (0x0C),     // After ADC sampling, filter the average number of samples (110)
    FILTER_1024           = (uint8_t) (0x0E),     // After ADC sampling, filter the average number of samples (111)
    SAMPLCK_250           = (uint8_t) (0x0),      // ADC sampling clk, 250KHz (00)
    SAMPLCK_500           = (uint8_t) (0x10),     // ADC sampling clk, 500KHz (01)
    SAMPLCK_1M            = (uint8_t) (0x20),     // ADC sampling clk, 1MHz (02)
    SAMPLCK_2M            = (uint8_t) (0x30),     // ADC sampling clk, 2MHz (03)
    ADC_MODE              = (uint8_t) (0x40),     // ADC sampling mode, 0: continue, 1: single
    ADC_START             = (uint8_t) (0x80),     // single mode, ADC interrupt complete flag bit, 1: complete, continue mode not use
    CLR_CLK_FILTER        = (FILTER_1024 | SAMPLCK_1M),
    ADC_1M_1024           = (FILTER_1024 | SAMPLCK_1M),
    ADC_1M_64             = (FILTER_64 | SAMPLCK_1M),
    ADC_250_256           = (FILTER_256 | SAMPLCK_250),
    ADC_START_SINGLE      = (ADC_MODE | ADC_START),
} ADCCON0_REG;

typedef enum
{
    ADCIF                 = (uint8_t) (0x01),     // single mode, ADC interrupt flag bit
    NTC0ISET_20           = (uint8_t) (0x00),     // NTC0 Internal current source tap setting, 20ua default(00), for ss888x
    NTC0ISET_40           = (uint8_t) (0x02),     // NTC0 Internal current source tap setting, 40ua(01), for ss888x
    NTC0ISET_60           = (uint8_t) (0x04),     // NTC0 Internal current source tap setting, 60ua(10), for ss888x
    NTC0EN                = (uint8_t) (0x20),     // NTC0 function, 0 disable, 1 enable
    ADCEN                 = (uint8_t) (0x40),     // adc interrupt function, 0 disable, 1 enable
    LOCKEN                = (uint8_t) (0x80),     // sample lock function, 0 disable, 1 enable
    ADCCON1_RESET         = (ADCIF | NTC0EN | ADCEN | LOCKEN | NTC0ISET_40 | NTC0ISET_60),
} ADCCON1_REG;

typedef enum
{
    ADCCON2_RESET,
    DIFFEN                = (uint8_t) (0x01),     // an4 and an5 diff enable(1), disable(0)
    IBUFEN                = (uint8_t) (0x02),     // input buffer function, 0 disable, 1 enable
    AN2CL                 = (uint8_t) (0x08),     // an2 central level, 0: 1.5V, 1:2.6V
    AN3CL                 = (uint8_t) (0x10),     // an3 central level, 0: 1.5V, 1:2.6V
    AN7CL                 = (uint8_t) (0x40),     // an7 central level, 0: 1.5V, 1:2.6V
} ADCCON2_REG;

typedef enum
{
    ADCCON3_RESET,
    AN4MODE               = (uint8_t) (0x01),     // an4 mode, 0: mirco voltage, 1:normal
    AN5MODE               = (uint8_t) (0x02),     // an5 mode, 0: mirco voltage, 1:normal
    AN4CL                 = (uint8_t) (0x04),     // an4 central level, 0: 1.5V, 1:2.6V
    AN5CL                 = (uint8_t) (0x08),     // an5 central level, 0: 1.5V, 1:2.6V
    VOFFSRC               = (uint8_t) (0x10),     // voltage offset input source, 0: 1.5V(VREF), 1:GND(0)
} ADCCON3_REG;

typedef enum
{
    NTC1EN                = (uint8_t) (0x01),     // NTC1 function, 0 disable, 1 enable, NTC1 for ss888x
    NTC1DST               = (uint8_t) (0x02),     // NTC1 Internal current source output control, 0 Output to the P01(AN3), 1 Output to the P16(AN5), NTC1 for ss888x
    NTC1DST_P01           = (uint8_t) (0x00),     // NTC1 Internal current source output control  P01(AN3)
    NTC1DST_P16           = (uint8_t) (0x02),     // NTC1 Internal current source output control  P16(AN5)
    NTC1ISET_18           = (uint8_t) (0x00),     // NTC1 Internal current source tap setting, 18ua default(0), 90ua(1) for ss888x
    NTC1ISET_90           = (uint8_t) (0x04),     // NTC1 Internal current source tap setting, 18ua default(0), 90ua(1) for ss888x
    NTC1ISET_RST          = (uint8_t) (0x04), 
} NTC1CON_REG;

typedef enum
{
    LDO_OC_60             = (uint8_t) (0x00),     // LDO over current function, current set 60ma(00) for ss888x
    LDO_OC_80             = (uint8_t) (0x01),     // LDO over current function, current set 80ma(default 01) for ss888x
    LDO_OC_100            = (uint8_t) (0x02),     // LDO over current function, current set 100ma(10) for ss888x
    LDO_OC_120            = (uint8_t) (0x03),     // LDO over current function, current set 120ma(11) for ss888x
    LDO_OC_RST            = (uint8_t) (0x03),
    LDO_1V8               = (uint8_t) (0x00),     // LDO function, Voltage set 1.8V(00) for ss888x
    LDO_2V5               = (uint8_t) (0x04),     // LDO function, Voltage set 2.5V(01) for ss888x
    LDO_3V0               = (uint8_t) (0x08),     // LDO function, Voltage set 3.0V(default 10) for ss888x
    LDO_3V3               = (uint8_t) (0x0C),     // LDO function, Voltage set 3.3V(11) for ss888x
    LDO_VRST              = (uint8_t) (0x0C),     // change ldo voltage, must closed over current protect module(OCEN)
    IBIASEN               = (uint8_t) (0x10),     // IBIAS Baseline enable control bit(LDO, OPA, NTC1 must use), 0 disable, 1 enable for ss888x
    BGREN                 = (uint8_t) (0x20),     // BGREN Baseline enable control bit(LDO, OPA, MLD must use), 0 disable, 1 enable for ss888x
    OCEN                  = (uint8_t) (0x40),     // LDO overcurrent protection enable control, 0 disable, 1 enable
    LDO_EN                = (uint8_t) (0x40),     //LDO enable control, 0 disable, 1 enable
    LDOCON0_CLR           = (uint8_t) (LDO_OC_RST | LDO_VRST | IBIASEN | BGREN | OCEN | LDO_EN),
} LDOCON0_REG;

typedef enum
{
    LDO_OC_STATE          = (uint8_t) (0x01),     // LDO over current state flag, if over occus, the flag is 1, util LDO closed
    LDO_HSEL              = (uint8_t) (0x08),     // LDO transient response optimization, 0 disable, 1 enable for ss888x
    LDO_OCMODE            = (uint8_t) (0x80),     // LDO over current mode, 0 normal, 1 High precision mode for ss888x
} LDOCON1_REG;

typedef enum
{
    DF_RD_EN              = (uint8_t) (0x01),     // Data flash read enable(01) for ss888x
    DF_WR_EN              = (uint8_t) (0x02),     // Data flash write enable(10) for ss888x
    DF_RW_NO              = (uint8_t) (0x03),     // Data flash read and write enable, Read and write prohibited(00/11) for ss888x
    DF_RD                 = (uint8_t) (0x04),     // Data flash read controller flag, active read(1), read over(0) for ss888x
    DF_WR                 = (uint8_t) (0x08),     // Data flash write controller flag, active write(1), write over(0) for ss888x
    UDBSEL                = (uint8_t) (0x80),     // UDB controller selector, Data flash(1), XDATA high 128BYTE(0) for ss888x
} UDBCON_REG;

typedef enum
{//U0CON
    UART0_RI              = (uint8_t) (0x01),     // uart recieve flag enable(1), disable(0)
    UART0_TI              = (uint8_t) (0x02),     // uart send tx flag enable(1), disable(0)
    UART0_BRPRE_DIV5      = (uint8_t) (0x00),     // System clock pre-div, div 5(0), only BRSRC = 1, UART0
    UART0_BRPRE_DIV13     = (uint8_t) (0x04),     // System clock pre-div, div 13(1) default, only BRSRC = 1
    UART0_REN             = (uint8_t) (0x10),     // uart recieve enable(1), disable(0)
    UART0_BR8             = (uint8_t) (0x20),     // uart bit8(BR) enable(1), disable(0), only BRSRC = 1
    UART0_BRSRC           = (uint8_t) (0x40),     // uart Baud rate generator choose tiemr0(1), choose inner SCLK(0)
    UART0_PAREN           = (uint8_t) (0x80),     // Serial port parity enable bit
} SCON_REG;

typedef enum
{
    UART1_RXEN            = (uint8_t) (0x01),     // uart1 rx enable(1), disable(0), if rxen = 0, fifo is clear
    UART1_TXEN            = (uint8_t) (0x02),     // uart1 tx enable(1), disable(0), if txen = 0, fifo is clear
    UART1_PARITY_NO       = (uint8_t) (0x00),     // Serial port parity enable bit, no(00)
    UART1_PARITY_OD       = (uint8_t) (0x04),     // Serial port parity enable bit, odd(01)
    UART1_PARITY_EV       = (uint8_t) (0x08),     // Serial port parity enable bit, even(10)
    UART1_BRPRE_DIV6      = (uint8_t) (0x00),     // System clock pre-div, div 6(0) default, UART1
    UART1_BRPRE_DIV13     = (uint8_t) (0x40),     // System clock pre-div, div 13(1)
} U1CON0_REG;

typedef enum
{
    UART1_RXFHFIE         = (uint8_t) (0x01),     // uart1 RX FIFO half full interrupt enable(1), disable(0)
    UART1_RXFNEIE         = (uint8_t) (0x02),     // uart1 RX FIFO not empty interrupt enable(1), disable(0)
    UART1_TXFHEIE         = (uint8_t) (0x04),     // uart1 TX FIFO half empty interrupt enable(1), disable(0)
    UART1_TXFEIE          = (uint8_t) (0x08),     // uart1 TX FIFO empty interrupt enable(1), disable(0)
    UART1_RXIDLEIE        = (uint8_t) (0x10),     // uart1 RX Idle status interrupt enable(1), disable(0)
    UART1_RXIDLE          = (uint8_t) (0x20),     // uart1 RX Idle status indicator, only read
} U1CON1_REG;

typedef enum
{
    UART1_RXFHF           = (uint8_t) (0x01),       // uart1 RX FIFO half full flag, yes(1), no(0), only read
    UART1_RXFNE           = (uint8_t) (0x02),       // uart1 RX FIFO not empty flag, yes(1), no(0), only read
    UART1_RXFO            = (uint8_t) (0x04),       // uart1 RX FIFO flag, yes(1), no(0), only read
    UART1_RER             = (uint8_t) (0x08),       // uart1 RX parity flag, error(1), no error(0), only read
    UART1_TXFHE           = (uint8_t) (0x10),       // uart1 TX FIFO half empty flag, yes(1), no(0), only read
    UART1_TXFE            = (uint8_t) (0x20),       // uart1 TX FIFO empty flag, yes(1), no(0), only read
    UART1_TXFF            = (uint8_t) (0x40),       // uart1 TX FIFO full flag, yes(1), no(0), only read
    UART1_BR8             = (uint8_t) (0x80),       // uart1 bit8(BR) enable(1), disable(0),
} U1STAT_REG;

typedef enum
{ 
    /** 
     * U1FIFOCON
     * When the data received in the FIFO is greater than or equal to the threshold, 
     * it is considered to be half full, and RXFHF is set 
     */
    UART1_RXFIFO_LVL_4    = (uint8_t) (0x10),       // uart1 RX FIFO half full flag, 4(00) default
    UART1_RXFIFO_LVL_5    = (uint8_t) (0x20),       // uart1 RX FIFO half full flag, 5(01)
    UART1_RXFIFO_LVL_6    = (uint8_t) (0x40),       // uart1 RX FIFO half full flag, 6(10)
    UART1_RXFIFO_LVL_7    = (uint8_t) (0x60),       // uart1 RX FIFO half full flag, 7(11)
    UART1_RXFIFO_LVL_CLR  = (uint8_t) (0x60),       // uart1 RX FIFO half full flag, clear
} U1FIFOCON_REG;

/**
 * \brief SPI data
 */
typedef enum
{
    SPI_EN                = (uint8_t) (0x01),       /* SPI module enable(1), disable(0) */
    SPI_OPEN_EN           = (uint8_t) (0x02),       /* if TX FIFO have data, occus CLK NSS */
    SPI_CPHA_1Edge        = (uint8_t) (0x00),       /* Data driven by SS pin is low */
    SPI_CPHA_2Edge        = (uint8_t) (0x04),       /* Data driven by the leading edge of SPI clock, then sampled on the trailing edg */
    SPI_CPOL_low          = (uint8_t) (0x00),       /* SPICLK is low when idle */
    SPI_CPOL_high         = (uint8_t) (0x08),       /* SPICLK is high when idle */
    SPI_first_bit_MSB     = (uint8_t) (0x00),       // spi send and receive bit sequence, MSB
    SPI_first_bit_LSB     = (uint8_t) (0x20),       // spi send and receive bit sequence, LSB

} SPICON0_REG;

typedef enum
{
    SPI_TX_ONLY           = (uint8_t) (0x01),       /* SPI only tx, enable(1), disable(0) */
    SPI_PUPD_EN           = (uint8_t) (0x02),       /* SPI NSS pullup(50KR), SCLK pulldown/pullup(50KR) according CPOL */
    SPI_HD_MODE           = (uint8_t) (0x80),       // spi mode, 3wire(1), 4wire(0)

} SPICON1_REG;

typedef enum
{
    SPI_baud_rate_div_2   = (uint8_t) (0x00),       /* SPI baud rate div, F(SPI) = F(SCLK)/2^(CLKDIV+1), 2(0000) */
    SPI_baud_rate_div_4   = (uint8_t) (0x01),       /* SPI baud rate div, F(SPI) = F(SCLK)/2^(CLKDIV+1), 4(0001) */
    SPI_baud_rate_div_8   = (uint8_t) (0x02),       /* SPI baud rate div, F(SPI) = F(SCLK)/2^(CLKDIV+1), 8(0010) */
    SPI_baud_rate_div_16  = (uint8_t) (0x03),       /* SPI baud rate div, F(SPI) = F(SCLK)/2^(CLKDIV+1), 16(0011) */
    SPI_baud_rate_div_32  = (uint8_t) (0x04),       /* SPI baud rate div, F(SPI) = F(SCLK)/2^(CLKDIV+1), 32(0100) */
    SPI_baud_rate_div_64  = (uint8_t) (0x05),       /* SPI baud rate div, F(SPI) = F(SCLK)/2^(CLKDIV+1), 64(0101) */
    SPI_baud_rate_div_128 = (uint8_t) (0x06),       /* SPI baud rate div, F(SPI) = F(SCLK)/2^(CLKDIV+1), 128(0110) */
    SPI_DATA_SIZE_4       = (uint8_t) (0x30),       /* SPI Data size 4bit */
    SPI_DATA_SIZE_5       = (uint8_t) (0x40),       /* SPI Data size 5bit */
    SPI_DATA_SIZE_6       = (uint8_t) (0x50),       /* SPI Data size 6bit */
    SPI_DATA_SIZE_7       = (uint8_t) (0x60),       /* SPI Data size 7bit */
    SPI_DATA_SIZE_8       = (uint8_t) (0x70),       /* SPI Data size 8bit(default) */
    SPI_DATA_SIZE_9       = (uint8_t) (0x80),       /* SPI Data size 9bit */
} SPICON2_REG;

typedef enum
{
    SPI_TX_LVL_1          = (uint8_t) (0x00),       /* SPI TX level interrupt trigger threshold, 1（000) */
    SPI_TX_LVL_2          = (uint8_t) (0x01),       /* SPI TX level interrupt trigger threshold, 2（001) */
    SPI_TX_LVL_3          = (uint8_t) (0x02),       /* SPI TX level interrupt trigger threshold, 3（010) */
    SPI_TX_LVL_4          = (uint8_t) (0x03),       /* SPI TX level interrupt trigger threshold, 4（011) */
    SPI_TX_LVL_5          = (uint8_t) (0x04),       /* SPI TX level interrupt trigger threshold, 5（100) */
    SPI_TX_LVL_6          = (uint8_t) (0x05),       /* SPI TX level interrupt trigger threshold, 6（101) */
    SPI_TX_LVL_7          = (uint8_t) (0x06),       /* SPI TX level interrupt trigger threshold, 7（110) */
    SPI_TX_LVL_8          = (uint8_t) (0x07),       /* SPI TX level interrupt trigger threshold, 8（111) */
    SPI_RX_LVL_1          = (uint8_t) (0x00),       /* SPI RX level interrupt trigger threshold, 1（000) */
    SPI_RX_LVL_2          = (uint8_t) (0x10),       /* SPI RX level interrupt trigger threshold, 2（001) */
    SPI_RX_LVL_3          = (uint8_t) (0x20),       /* SPI RX level interrupt trigger threshold, 3（010) */
    SPI_RX_LVL_4          = (uint8_t) (0x30),       /* SPI RX level interrupt trigger threshold, 4（011) */
    SPI_RX_LVL_5          = (uint8_t) (0x40),       /* SPI RX level interrupt trigger threshold, 5（100) */
    SPI_RX_LVL_6          = (uint8_t) (0x50),       /* SPI RX level interrupt trigger threshold, 6（101) */
    SPI_RX_LVL_7          = (uint8_t) (0x60),       /* SPI RX level interrupt trigger threshold, 7（110) */
    SPI_RX_LVL_8          = (uint8_t) (0x70),       /* SPI RX level interrupt trigger threshold, 8（111) */
    SPI_FIFO_RST          = (uint8_t) (0x80),       /* SPI RX/TX FIFO reset(1) */
} SPIFCON_REG;

typedef enum
{
    SPI_TX_FIFO_INT       = (uint8_t) (0x01),       /* SPI tx FIFO interrupt , enable(1), disable(0) */
    SPI_RX_FIFO_INT       = (uint8_t) (0x02),       /* SPI rx FIFO interrupt , enable(1), disable(0) */
} SPIINTEN_REG;

typedef enum
{
    SPI_TX_FIFO_FLAG      = (uint8_t) (0x01),       /* SPI tx FIFO flag , send over(1), sending(0) */
    SPI_RX_FIFO_FLAG      = (uint8_t) (0x02),       /* SPI rx FIFO flag , have data(1), not(0) */
} SPIINTSTAT_REG;

typedef enum
{
    PRCEN                 = (uint8_t) (0x10),       /* 可编程振荡器PRC使能位： enable(1),disable(1) */
    PRCFC_1700KHz         = (uint8_t) (0x00),       /* 可编程振荡器PRC的中心频率选择, 1.7MHz(00) */
    PRCFC_2400KHz         = (uint8_t) (0x40),       /* 可编程振荡器PRC的中心频率选择, 2.4MHz(01) */
    PRCFC_3000KHz         = (uint8_t) (0x80),       /* 可编程振荡器PRC的中心频率选择, 3.0MHz(10) */
    PRCFC_3300KHz         = (uint8_t) (0xC0),       /* 可编程振荡器PRC的中心频率选择, 3.3MHz(11) */
    PRCFC_CLR             = (uint8_t) (0xC0),
}  PRCCON0_REG;

typedef enum
{
    PRCDIV_1              = (uint8_t) (0x00),       /* PRC输出时钟分频比, /1 (00) */
    PRCDIV_8              = (uint8_t) (0x01),       /* PRC输出时钟分频比, /8 (01) */
    PRCDIV_16             = (uint8_t) (0x02),       /* PRC输出时钟分频比, /16 (10) */
    PRCDIV_32             = (uint8_t) (0x03),       /* PRC输出时钟分频比, /32 (11) */
    PRCDIV_CLR            = (uint8_t) (0x03),
    PRODUTY_EN            = (uint8_t) (0x04),       /* 可编程频率输出（PFO）占空比调节使能位 0，不使能（不调节占空比，占空比固定为50%）1，使能 */
    PRCFREQE_8T10_CLR     = (uint8_t) (0xE0),       /* 可编程振荡器PRC输出频率微调档位高3 */

}  PRCCON1_REG;

typedef enum
{
    SSEN                  = (uint8_t) (0x01),       /* 展频（Spread Spectrum）使能控制位 */
    SSRANGE_1             = (uint8_t) (0x00),       /* 展频（Spread Spectrum）范围选择，000，±1档 */
    SSRANGE_2             = (uint8_t) (0x02),       /* 展频（Spread Spectrum）范围选择，001，±2档 */
    SSRANGE_4             = (uint8_t) (0x04),       /* 展频（Spread Spectrum）范围选择，010，±4档 */
    SSRANGE_8             = (uint8_t) (0x06),       /* 展频（Spread Spectrum）范围选择，011，±8档 */
    SSRANGE_16            = (uint8_t) (0x08),       /* 展频（Spread Spectrum）范围选择，100，±16档 */
    SSRANGE_32            = (uint8_t) (0x0A),       /* 展频（Spread Spectrum）范围选择，101，±32档 */
    SSRANGE_64            = (uint8_t) (0x0C),       /* 展频（Spread Spectrum）范围选择，110，±64档 */
    SSRANGE_128           = (uint8_t) (0x0E),       /* 展频（Spread Spectrum）范围选择，111，±128档 */
    SSRANGE_CLR           = (uint8_t) (0x0E),
    SSSPEED_0             = (uint8_t) (0x00),       /* 展频（Spread Spectrum）调节速度选择（档位越低，调节速度越低），00，档位0 */
    SSSPEED_1             = (uint8_t) (0x10),       /* 展频（Spread Spectrum）调节速度选择（档位越低，调节速度越低），01，档位1 */
    SSSPEED_2             = (uint8_t) (0x20),       /* 展频（Spread Spectrum）调节速度选择（档位越低，调节速度越低），10，档位2 */
    SSSPEED_3             = (uint8_t) (0x30),       /* 展频（Spread Spectrum）调节速度选择（档位越低，调节速度越低），11，档位3 */
    SSSPEED_CLR           = (uint8_t) (0x30),
    SFMODE                = (uint8_t) (0x40),       /* 展频（Spread Spectrum）模式选择：0, 连续模式  1, 断续模式 */
    PRCCON2_CLR           = (uint8_t) (0x7F),
}  PRCCON2_REG;

typedef enum
{
    DLLEN                 = (uint8_t) (0x01),       /* DLL使能控制位, 0 不使能， 1 使能 */
    CLKSRC                = (uint8_t) (0x02),       /* DLL时钟源选择, 0 PRCCLK， 1 SCLK */
    HPWM4IN1              = (uint8_t) (0x04),       /* CC0~3 4路PWM是否一起微调占空比：0，仅CC0和CC1可独立配置为HPWM微调占空比  1，CC0~3统一共同配置为同频同占空比同占空比微调的HPWM */
    DLLLOCK               = (uint8_t) (0x08),       /* DLL是否成功锁定标志：0，没有锁定成功，1，锁定成功 */
    DUTY0_CLR             = (uint8_t) (0x03),       /* 当CLKSRC=0（且PRCDIV=00,SSEN=0）的时候，DUTY0可用于设置PFO的占空比：DPFO = (DUTY0 + 1) / 16 */
    DLLCON0_CLR           = (uint8_t) (0xFF)
}  DLLCON0_REG;

typedef enum
{
    DLLFREQ_1T3MHz        = (uint8_t) (0x00),       /* DLL频率范围（软件需要根据SCLK的频率选择合适的频率范围）00，1~3MHz */
    DLLFREQ_2T6MHz        = (uint8_t) (0x08),       /* DLL频率范围（软件需要根据SCLK的频率选择合适的频率范围）01，2~6MHz */
    DLLFREQ_4T12MHz       = (uint8_t) (0x10),       /* DLL频率范围（软件需要根据SCLK的频率选择合适的频率范围）10，4~12MHz */
    DLLFREQ_CLR           = (uint8_t) (0x18),
}  DLLCON1_REG;

/**
 * @brief gpio io mode, 0 is P00/P10/P20 status, 1: output 0: input
 * 
 */
#define    GPIO_0_OUTPUT           (0x01)
#define    GPIO_0_INPUT            (0x00)

#define    GPIO_1_OUTPUT           (0x02)
#define    GPIO_1_INPUT            (0x00)

#define    GPIO_2_OUTPUT           (0x04)
#define    GPIO_2_INPUT            (0x00)

#define    GPIO_3_OUTPUT           (0x08)
#define    GPIO_3_INPUT            (0x00)

#define    GPIO_4_OUTPUT           (0x10)
#define    GPIO_4_INPUT            (0x00)

#define    GPIO_5_OUTPUT           (0x20)
#define    GPIO_5_INPUT            (0x00)

#define    GPIO_6_OUTPUT           (0x40)
#define    GPIO_6_INPUT            (0x00)

#define    GPIO_7_OUTPUT           (0x80)
#define    GPIO_7_INPUT            (0x00)

#define    P0_ALL_INPUT            (0x0)
#define    P1_ALL_INPUT            (0x0)
#define    P1_EFR_INPUT            (0x0)
#define    P2_EFR_INPUT            (0x0)
#define    P2_EXT_INPUT            (0x0)


/**
 * @brief gpio io pull mode  0: disable 1: enable
 * 
 */
#define    GPIO_0_PULLUP            (0x01)
#define    GPIO_1_PULLUP            (0x02)
#define    GPIO_2_PULLUP            (0x04)
#define    GPIO_3_PULLUP            (0x08)
#define    GPIO_4_PULLUP            (0x10)
#define    GPIO_5_PULLUP            (0x20)
#define    GPIO_6_PULLUP            (0x40)
#define    GPIO_7_PULLUP            (0x80)
#define    P0_ALL_PULLUP            (0xFF)
#define    P1_ALL_PULLUP            (0x1F)
#define    P1_EFR_PULLUP            (0xE0)
#define    P2_EFR_PULLUP            (0x07)
#define    P2_EXT_PULLUP            (0xF9)

/**
 * @brief gpio io pull mode  0: disable 1: enable
 * 
 */

#define    GPIO_0_PULLDOWN            (0x01)
#define    GPIO_1_PULLDOWN            (0x02)
#define    GPIO_2_PULLDOWN            (0x04)
#define    GPIO_3_PULLDOWN            (0x08)
#define    GPIO_4_PULLDOWN            (0x10)
#define    GPIO_5_PULLDOWN            (0x20)
#define    GPIO_6_PULLDOWN            (0x40)
#define    GPIO_7_PULLDOWN            (0x80)
#define    P0_ALL_PULLDOWN            (0xFF)
#define    P1_ALL_PULLDOWN            (0x1F)
#define    P1_EFR_PULLDOWN            (0xE0)
#define    P2_EFR_PULLDOWN            (0x07)
#define    P2_EXT_PULLDOWN            (0xF9)


/**
 * @brief ADC channel
 * default VBAT is on IBAT and VREF is off 
 */

#define    ADC_NO_USE    (0)
#define    VBAT          (0x01)
#define    IBAT          (0x02)
#define    AN2           (0x04)
#define    AN3           (0x08)
#define    AN4           (0x10)
#define    AN5           (0x20)
#define    VREF          (0x40)
#define    AN7           (0x80)

/**
 * @brief PWM channel
 *
 */

#define    CMP_NO_USE               (0)
#define    CMP0                     (1)
#define    CMP1                     (2)


/**
 * @brief NTC channel
 *
 */
#define    NTC_NO_USE       (0)
#define    NTC              (0x20)     // NTC function 0 disable 1 enable

/**
 * @brief PWM channel
 *
 */
#define    PWM_NO_USE           (0)
#define    PWM0                 (0x01)
#define    PWM1                 (0x02)

/**
 * @brief CC channel
 *
 */

#define    CC_NO_USE                (0)
#define    CC0                      (0x01)
#define    CC1                      (0x02)
#define    CC2                      (0x04)
#define    CC3                      (0x08)

/**
 * @brief PFO channel
 *
 */
#define    PFO_NO_USE               (0)
#define    PFO                      (0x01)

/**
 * @brief touch source channel
 *
 */

#define    TS_NO_USE                (0)
#define    TS0                      (0x01)
#define    TS1                      (0x02)
#define    TS2                      (0x04)
#define    TS3                      (0x08)
#define    TS4                      (0x10)
#define    TS5                      (0x20)

/**
 * @brief uart channel
 *
 */

#define    UART_NO_USE              (0)
#define    TX0                      (0x01)      // pullup
#define    RX0                      (0x02)
#define    MT0                      (0x04)      // pullup, init rx mode,  user should switch between TX or RX mode manually.
#define    TX1                      (0x10)      // pullup, not init, user should switch between TX or RX mode manually.
#define    RX1                      (0x20)      // not init, user should switch between TX or RX mode manually.
#define    MT1                      (0x40)      // pullup, not init, user should switch between TX or RX mode manually.
/**
 * @brief EINT channel
 *
 */

#define    EINT_NO_USE              (0)
#define    EINT0                    (0x01)
#define    EINT1                    (0x02)

/**
 * @brief SPI channel
 *
 */

#define    SPI_NO_USE              (0)
#define    SPI_SS                  (0x01)
#define    SPI_SCK                 (0x02)
#define    SPI_MISO                (0x04)
#define    SPI_MOSI                (0x08)

/**   GPIO_MODE    **/
#define    GPIO_NO_USE             (0)
#define    GPIO_MODE_OUTPUT        (1)      /*!< Output Push Pull Mode                 */
#define    GPIO_MODE_OUTPUT_OD     (2)      /*!< Output Open Drain Mode                */
#define    GPIO_MODE_INPUT         (3)      /*!< Input Floating Mode                   */
#define    GPIO_MODE_NTC           (4)      /*!< NTC Mode  */
#define    GPIO_MODE_ADC           (5)      /*!< ADC Mode  */
#define    GPIO_MODE_PWM           (6)      /*!< PWM Mode  */
#define    GPIO_MODE_CC            (7)      /*!< CC Mode  */
#define    GPIO_MODE_CMP           (8)      /*!< CMP Mode  */
#define    GPIO_MODE_TS            (9)      /*!< TS Mode  */
#define    GPIO_MODE_TX0           (10)     /*!< UART0 TX Mode  */
#define    GPIO_MODE_RX0           (11)     /*!< UART0 RX  Mode  */
#define    GPIO_MODE_MT0           (12)     /*!< UART0 RX/TX Mode  */
#define    GPIO_MODE_TX1           (13)     /*!< UART1 TX Mode  */
#define    GPIO_MODE_RX1           (14)     /*!< UART1 RX  Mode  */
#define    GPIO_MODE_MT1           (15)     /*!< UART1 RX/TX Mode  */
#define    GPIO_MODE_EINT          (16)     /*!< EINT Mode  */
#define    GPIO_MODE_SPI           (17)     /*!< SPI Mode  */
#define    GPIO_MODE_PFO           (18)     /*!< PFO Mode  */

/** @defgroup GPIO_pull_define GPIO pull define
  * @brief GPIO Pull-Up or Pull-Down Activation
  * @
  */

#define    GPIO_NOPULL        (0)          /*!< No Pull-up or Pull-down activation  */
#define    GPIO_PULLUP        (1)          /*!< Pull-up activation                  */
#define    GPIO_PULLDOWN      (2)          /*!< Pull-down activation                */

#endif /* __TYPES_H__ */

